Recent research projects
Signature Extraction for Hardware Monitoring to Secure Processing in Embedded Systems
In this project we have proposed a framework to exploit external system behavior such as power consumption, execution cycles, and temperature as signatures by which we can detect any deviation from expected behavior due to security attack. In this thesis, we have shown that using machine learning and artificial intelligence approaches is a viable solution to detect security attacks based on the mentioned external behavior. Our simulation results using a real code injection attack shows that these approaches have and accuracy between 95% to 100% depending on the employed approach and the benchmark program.
Energy-Efficient Fault-Tolerant Task Scheduling for Real-Time Multiprocessor Systems
By considering periodic real-time tasks in multiprocessor systems, we are able to propose a novel online scheduling technique which tackles this issue. To achieve optimal system design in terms of reliability, the system must be resilient to both transient and permanent faults. So, in addition to transient faults which are more frequent, we also consider the permanent faults. The main idea behind of our method is to schedule multiple copies of the same task (replicas) in different processors in a moderate speed so that the overlap between replicas is minimized. In this approach not only can reach the system’s original reliability, but also can obtain further levels of fault tolerance. Moreover, according to the task’s reliability target, tasks can have different replication numbers. Our experimental results reveal a significant energy saving (up to 45%) in comparison with state-of-the-art reliability oriented scheme while offering the desired target reliability.
An Architecture Level Approach for Lifetime Enhancement of PCM Main Memory
Proposing a technique to swap data between memory lines for reducing bit flips, is the main goal of this project. The proposed swapping technique finds the best place to write a chunk of data among a limited set of lines to minimize the amount of required bit flips. The swapping operation is carried out online, without any prior profiling of data. This technique is hidden from the programmer and doesn’t impact other levels of memory hierarchy. Moreover, it doesn’t require major modifications of existing solutions and works only by the addition of a proposed circuitry. In addition, this technique is additive to various other architectures aiming at PCM lifetime enhancement.
A New Countermeasure against DFA Fault Attacks in Cryptosystems
Securing AES encryption algorithm against differential fault attacks is the main purpose of this project. To achieve this goal, we have used temporal redundancy for non-linear operation and information redundancy for linear operations. In order to take advantage of the computational complexity and fault propagation differences between these two types of operations and consequently improve fault detection against fault events, we have used 8-bits, 16-bits and 32-bits parity codes.
Using MTJ for Design New Logic circuit and Enhance CMOS Based circuit performance
In this project, we study the effect of MTJ on dynamic and static power consumption and by comparing result of previously worked idea with our own solution, we observe dynamic power consumption reduction only in comparison with MTJ based circuit but static power consumption reduced totally in comparison with CMOS based circuit. In other hand using MLUT based circuit lead circuit are reduction and capability to increase circuit density. According to simulation result, we can conclude using MLUT based circuit can reduce static, so if we plane to replace CMOS with MTJ, we need further improvement in MTJ operational properties